September 2-4 – Hilton London Tower Bridge (Hybrid Event)
Computing hardware has become an attractive attack surface, either due to unintentional design flaws or malicious design modifications. Hardware designers and automation tool developers alike are challenged to understand the different hardware security threats in order to incorporate effective countermeasures into robust hardware design, verification, and testing. The most common targets in such adversary attacks are secure architectures, cryptographic primitives, and intellectual property (IP) by counterfeiting. Moreover, as more Internet of Things (IoT) applications are emerging, vulnerabilities to cyberattacks are created as well, with new hardware-based defense mechanisms for smart systems and devices being in need. With well-known hardware security threats such as Hardware Trojans (HT), Reverse Engineering (RE), and covert and side channels continuously advancing, novel attacks targeting remote, cross-layer liabilities also become prevalent.
At the same time, hardware solutions have proven to be highly efficient when it comes to security assurance. Two such security primitives are True Random Number Generators (TRNGs) and Physical Unclonable Functions (PUFs), which offer protection against spoofing and tampering attacks. Lightweight cryptographic modules are especially useful as an increasing number of devices in the IoT with resource constraints require strong security and mutual authentication schemes. Hardware implementation of cryptographic primitives can offer flexibility, power efficiency, and the ability of parallel processing. Since the physical layer often acts as the base of trust in a system, a promising research direction towards state-of-the-art hardware security solutions is being formed.
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Prospective authors are encouraged to submit previously unpublished contributions from a broad range of topics, which include but are not limited to the following:
• Architectures and Applications: 5G/6G, Healthcare, IoT etc
• Attacks: Implementations and Countermeasures
• Constrained and Trusted Environments
• Cryptanalysis for Hardware
• Cryptographic Primitives and Lightweight Cryptography
• Hardware Crypto-Processors, System-on-Chip (SoC) and Reconfigurable Designs
• Hardware Obfuscation
• Networks, Protocols and Communications: Hardware Integrations
• PUFs, Trojans and TRNGs on Hardware
• Reverse Engineering
• Smart Cards Cybersecurity
• Trust and Anti-Counterfeiting;
Paper submission deadline: June 3 June 30, 2024 AoE
Authors’ notification: July 3 July 14, 2024 AoE
Camera-ready submission: July 14 July 20, 2024 AoE
Early registration deadline: July 20, 2024 AoE
Workshop date: September 2-4, 2024
The workshop’s proceedings will be published by IEEE and will be included in IEEE Xplore. The guidelines for authors, manuscript preparation guidelines, and policies of the IEEE CSR conference are applicable to HACS 2024 workshop. Please visit the authors’ instructions page for more details. When submitting your manuscript via the conference management system, please make sure that the workshop’s track 2T4 HACS is selected in the Topic Areas drop down list.
Workshop chairs
Nicolas Sklavos, University of Patras (GR)
Valeria Loscri, Inria-Lille, Nord Europe (FR)
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Program committee
Giovanni Agosta, Politecnico di Milano (IT)
Allesandro Brighente, University of Padova (IT)
Ileana Buhan, Radboud University (NL)
Ricardo Chaves, INESC-ID/IST/ULisboa (PT)
Pascal Cotret, Lab-STICC (FR)
Soumyajit Dey, IT Kharagpur (IN)
Giorgio Di Natale, TIMA – CNRS (FR)
Zoya Dyka, IHP – Leibniz-Institut für innovative Mikroelektronik (DE)
Alexander Fish, Bar Ilan University (IL)
Apostolos Fournaris, Industrial Systems Institute/Research Center ATHENA (GR)
Basel Halak, University of Southampton (UK)
Ivgen Kabin, IHP – Leibniz-Institut für innovative Mikroelektronik (DE)
Elif Bilge Kavun, University of Passau (DE)
Osnat Keren, Bar Ilan University (IL)
Paris Kitsos, University of Peloponnese (GR)
Odysseas Koufopavlou, University of Patras (GR)
Ulrich Kühne, Télécom Paris / Institut polytechnique de Paris (FR)
Peter Langendoerfer, HP & BTU Cottbus-Senftenberg (DE)
Francesco Leporati, University of Pavia (IT)
Alla Levina, LETI University (RU)
Marco Macchetti, Qualcomm Technologies (CH)
Nikolay Moldovyan, St. Petersburg Federal Research Center of the Russian Academy of Sciences (RU)
Maria Mushtaq, Telecom Paris (FR)
Francesco Regazzoni, University of Amsterdam/Università della Svizzera italiana (NL/CH)
Vincent Rijmen, KU Leuven/University of Bergen (BE/NO)
Georgios Selimis, AXELERA AI BV (NL)
Stavros Shiales, University of Portsmouth (UK)
Leonel Sousa, INESC-ID, Instituto Superior Técnico, Universidade de Lisboa (PT)
Sara Tehranipoor, West Virginia University (US)
Guzin Ulutas, Karadeniz Technical University (TR)
Selma Yahia, Inria-Lille, Nord Europe (FR)
Sherali Zeadally, University of Kentucky (US)